1. Field of the Invention
The present invention relates to a liquid crystal display device with a color image display function, and in particular to an active-type liquid crystal display device.
2. Description of Related Art
Televisions and various other image display devices which have a liquid crystal display of 5 to 75 cm in diagonal length are commercially available in mass quantity through the progress in recent years in micro-fabrication, liquid crystal material, high-density packaging technology, and other such technologies. In addition, color displays can easily be obtained by forming an RGB color layer on one of the two glass substrates composing the liquid crystal panel. In particular, in a so-called active liquid crystal panel with a switching element inside each pixel, there is little cross-talk, the response rate is high, and images with a high contrast ratio are guaranteed.
For these liquid crystal displays (liquid crystal panels), the matrix organization generally comprises around from 200 to 1200 scan lines and 300 to 1600 signal lines, but recently increases in screen size and definition are progressing simultaneously in response to the increase in display capacity.
FIG. 9 shows a state of liquid crystal panel mounting in which electric signals are provided to an image display part using packaging means such as COG (Chip-On-Glass) in which a conductive adhesive is used to connect a semiconductor integrated-circuit chip 3 for supplying a drive signal to electrode terminals 5 for scan lines formed on one of the transparent insulating substrates composing a liquid crystal panel 1, for example a glass substrate 2, or TCP (Tape-Carrier-Package) for fixing a TCP film 4, to electrode terminals 6 for signal lines using pressure and a suitable adhesive including a conductive medium using, for example, a thin polyimide-base plastic film with a copper foil terminals plated with gold or solder as a base. Herein, both of these mounting methods are shown at the same time for convenience, but in actual practice, either method may be arbitrarily selected.
Wire paths connecting the interval between the pixels in the image display area positioned nearly in the center of a liquid crystal panel 1 and electrode terminals 5 and 6 for scan lines and signal lines are 7 and 8, and do not necessarily need to be constructed of the same conductive material as the electrode terminals 5 and 6. 9 is a color filter or an opposing glass that is another transparent insulating substrate having transparent conductive opposing electrodes on its opposing side, which is common to all the liquid crystal cells.
FIG. 10 shows an equivalent circuit of an active-type liquid crystal display device with an insulating gate-type transistor 10 disposed as a switching element at each pixel. In the figure, 11 (7 in FIG. 9) is a scan line, 12 (8 in FIG. 9) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is treated as a capacitance element electrically. The elements drawn with solid lines are formed on the glass substrate 2, one of the glass substrates composing the liquid crystal panel, and opposing electrode 14 drawn with dotted lines common to all the liquid crystal cells 13 is formed on the main surface opposite the other glass substrate 9. If the “off” resistance of the insulating gate-type transistor 10 or the resistance of the liquid crystal cell 13 is low, or if gradation in the displayed image is to be emphasized, circuitry means may be introduced such as adding an auxiliary storage capacitor 15 in parallel with the liquid crystal 13 as a load to increase the time constant thereof 16 is a storage capacitor line forming a mother line common to the storage capacitors 15.
FIG. 11 shows a cross-sectional view of the essential part of an image display part of a liquid crystal display device. The two glass substrates 2 and 9 composing the liquid crystal panel 1 are formed separated by a specified distance of several μm by a spacer material (not illustrated) such as pillar-shaped resin spacers formed on a color filter 9, plastic fibers, or plastic beads, and that gap is a closed spaced sealed by a sealing material and an end-sealing material made from an organic resin (neither of which are illustrated) at the periphery of the glass substrate 9, and the gap is filled with liquid crystal 17.
To obtain a color display, a thin organic film about 1 to 2 μm thick including either a dye or pigment or both called a color layer 18 is deposited on the closed space side of the glass substrate 9, providing a color display function, in which case the glass substrate 9 may also be referred to by the name a color filter (abbreviated as CF). Depending on the property of the liquid crystal material 17, a polarization plate 19 is attached to the top of the glass substrate 9 or the bottom of the glass substrate 2 or both, so the liquid crystal panel 1 functions as an electro-optical element. TN (Twisted-Nematic)-type liquid crystal material is currently used in most liquid crystal panels available commercially, and two polarization plates 19 are normally required. Although not illustrated, a back light source is disposed as a light source in the transmission-type liquid crystal panel, irradiating white light from below.
A thin polyimide-type resin film 20 about 0.1 μm thick, for example, formed on the two glass substrates 2 and 9 and in contact with the liquid crystal 17 is an alignment film for orientating liquid crystal molecules in a fixed direction. 21 is a drain electrode (wire) for connecting a drain of the insulating gate-type transistor 10 and a transparent conductive pixel electrode 22, and is often formed at the same time as a signal line (source line) 12. A semiconductor layer 23 is positioned between the signal line 12 and the drain electrode 21 and is described in further detail below. A thin Cr film layer 24 about 0.1 μm thick formed at the interface of the adjacent color layer 18 on the a color filter 9 is a light shield material for preventing external light from radiating on the semiconductor layer 23, the scan line 11, or the signal line 12. This is an established technology referred to as black matrix (abbreviated as BM).
Here, a description is given of the structure of an insulating gate-type transistor as a switching element and its manufacturing method. Two types of insulating gate-type transistors are currently used commonly, one of which will be introduced as a prior art example and be referred to as an etch-stop type. FIG. 12 is a plan view of a unit pixel of an active substrate (semiconductor devices for display devices) composing a conventional liquid crystal panel. Cross-section views of lines A-A′, B-B′ and C-C′ in FIG. 12(e) are shown in FIG. 13. The manufacturing process thereof is described briefly below.
First, a first metal layer about 0.1 to 0.3 μm thick is deposited over the main surface of a glass substrate 2, product name 1737 manufactured by Corning, Incorporated, for example, about 0.5 to 1.1 mm thick as an insulating substrate with high transparency, chemical-resistance, and heat-resistance, and scan lines doubling as gate electrodes 11A and storage capacitor lines 16 are selectively formed using photosensitive resin patterns with micro-fabrication technology as shown in FIG. 12(a) and FIG. 13(a). The material for the scan line may be selected taking into consideration the combined properties of heat-resistance, chemical-resistance, hydrofluoric acid resistance, and conductance, though a metal with a high heat-resistance such as a Cr, Ta and an alloy thereof such as MoW is generally used.
While using Al (aluminum) as the material for the scan lines is reasonable for lowering the resistance value of the scan lines in response to the larger screens and higher definitions of liquid crystal panels, by itself, Al has a low heat-resistance, so adding an oxide layer (Al2O3) in anodization of the Al surface or laminating with Cr, Ta or Mo or a silicide thereof which are the said heat-resistance metals is currently the general technology in use. In other words, the scan lines 11 are constructed of one or more metal layers.
Next, a PCVD (plasma CVD) equipment is used to successively deposit three thin film layers about 0.3, 0.05, and 0.1 μm thick, for example, comprising a first SiNx (silicon nitride) layer 30 composing a gate insulating layer, a first amorphous silicon (a-Si) layer 31 composing a channel for an insulating gate-type transistor including almost no impurities, and a second SiNx layer 32 composing an insulating layer for protecting the channel, over the entire surface of the glass substrate 2, and micro-fabrication technology is used to selectively leave the second SiNx layer above the gate electrodes 11A narrower than the gate electrode 11A to form protection layers 32D as shown in FIG. 12(b) and FIG. 13(b), exposing the first amorphous silicon layer 31.
Continuing, the second amorphous silicon layer 33 including phosphorous, for example as an impurity, is deposited similarly about 0.05 μm thick, for example, over the entire surface using the PCVD equipment. Then, a thin film layer 34 of Ti, Cr, Mo, or the like, for example, is deposited as a heat-resistant metal layer about 0.1 μm thick, an Al thin film layer 35 about 0.3 μm thick is deposited as a low-resistance wiring layer, and a Ti thin film layer, for example, is deposited as an intermediate conductive layer about 0.1 μm thick. Drain electrodes 21 of insulating gate-type transistors comprising a laminate of these three thin film layers 34A, 35A, and 36A, which are source-drain wire materials, and signal lines 12 doubling as source electrodes are selectively formed with micro-fabrication technology using photosensitive resin patterns as shown in FIG. 12(c) and FIG. 13(c). This selective patterning is made by successively etching the Ti thin film layer 36, the Al thin film layer 35, and the Ti thin film layer 34 using the photosensitive resin patterns used in forming the source-drain wires as masks, and then removing the second amorphous silicon layer 33 between the source-drain electrodes 12 and 21 to expose the protective insulating layers 32D as well as removing the first amorphous silicon layer 31 in other regions to expose the gate insulating layer 30. Because the second SiNx layers 32D (protective insulating layers, etch-stop layers), which are layers for protecting the channels, are thus present, and the etching of the second amorphous silicon layer 33 automatically ends, this manufacturing method is called etch-stop.
Source-drain electrodes 12 and 21 are formed partly (a few μms) overlapped on a flat surface with protective insulating layers 32D so that the insulating gate type transistors do not form offset structures. This overlapping is better when small, for it works electrically as parasitic capacitance. However, its practical value is only about 2 μms for it is determined by the overlay accuracy of mask aligners (exposure equipments), the accuracy of photo-masks, the expansion coefficient of glass substrates, and the temperature of glass substrates during exposure.
Furthermore, after removing the said photosensitive resin patterns, a SiNx layer about 0.3 μm thick is deposited over the entire surface of the glass substrate 2 similarly to the gate insulating layer as a transparent insulating layer using the PCVD equipment to form a passivation insulating layer 37, the passivation insulating layer 37 is selectively removed using photosensitive resin patterns with micro-fabrication technology to form openings 62 on the drain electrodes 21 and openings 63 on the scan lines 11 and openings 64 on the signal lines 12 outside an image display area to expose the drain electrodes 21, part 5 of the scan lines 11 and part 6 of the signal lines 12, respectively as shown in FIG. 12(d) and FIG. 13(d). Openings 65 are similarly formed on the electrode patterns bundled and in parallel with the storage capacitor lines 16 to expose part thereof.
Finally, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide), for example, is deposited as a transparent conductive layer about 0.1 to 0.2 μm thick using an SPT or other vacuum film-depositing equipment, and pixel electrodes 22 are selectively formed on the passivation insulating layer 37 containing the openings 62 using photosensitive resin patterns with micro-fabrication technology to complete the active substrate 2 as shown in FIG. 12(e) and FIG. 13(e). Part of the scan lines 11 exposed in the openings 63 may be used as the electrode terminals 5, and part of the signal lines 12 exposed in the openings 64 as the electrode terminals 6, and the electrode terminals 5A and 6A made from ITO on the passivation insulating layer 37 containing the openings 63 and 64 may be selectively formed as illustrated, but transparent conductive short lines 40 are ordinarily formed at the same time connected between the electrode terminals 5A and 6A. The reason for this is so a high resistance can be made as a measure against static electricity by forming the interval between the electrode terminals 5A/6A and the short wires 40 into long-narrow striped forms to increase the resistance (not illustrated). Similarly, electrode terminals are formed on the storage capacitor lines 16 containing the openings 65, though a number thereof is not provided.
If wiring resistance of the signal wire 12 is not a problem, a low-resistance wire layer 35 made from Al is not necessarily required, in which case it is possible to simplify the layers of the source-drain wires 12 and 21 by selecting heat-resistant metal material such as Cr, Ta, or MoW. Ensuring an electrical connection with the second amorphous silicon layer using a heat-resistant metal layer is thus more important for the source-drain wires; the heat resistance of an insulating gate-type transistor is described in detail in Unexamined Patent Application Number H 7-74368 [i.e., 1995-74368] as an example of prior art. A region 50 (a right-slanting oblique portion) over which the storage capacitor line 16 and the drain electrode 21 are superimposed in a planar manner via the gate insulating layer 30 in FIG. 12 (c) forms a storage capacitor 15, though a detailed description is omitted here.
A detailed history of the five-mask process described above is omitted, but it is obtained as the result of streamlining the semiconductor islanding processing and decreasing the number of contact-formation processes. Photo-masking, which initially required seven to eight times, has been reduced to the current five layers by the introduction of dry etching technology, which greatly contributes to the decreasing process costs. It is a well-known target of development that lowering the process cost in the manufacture of the active substrate and the material cost in the panel assembly and module packaging processes is effective in lowering the production costs of liquid crystal display devices. To lower process costs, either process may be eliminated to make the process shorter, or inexpensive process development or replacement to inexpensive process is available. Here, four-mask process resulting in an active substrate with four photo-masks is described as an example of eliminating processes. The photo-etching process is eliminated by introducing half-tone exposure technology. FIG. 14 shows a plan view of a unit pixel in an active substrate corresponding to the four-mask process. The cross-section views of lines A-A′, B-B′ and C-C′ in FIG. 14(e) are shown in FIG. 15. As already mentioned, two types of insulating gate-type transistors are commonly in use. Here, a channel etch-type insulating gate-type transistor is selected.
First, a first metal layer about 0.1 to 0.3 μm thick is deposited on the main surface of the glass substrate 2 using the SPT or other vacuum film-depositing equipment similar to as done in the five-mask process, and the storage capacitor lines 16 and scan lines 11 doubling as the gate electrodes 11A are selectively formed using photosensitive resin patterns with micro-fabrication technology as shown in FIG. 14(a) and FIG. 15(a).
Next, three thin film layers comprising the SiNx layer 30 composing a gate insulating layer, a first amorphous silicon layer 31 composing a channel for an insulating gate-type transistor including hardly any impurities, and a second amorphous silicon layer 33 composing source-drain for an insulating gate-type transistor including impurities are successively deposited about 0.3 to 0.2 to 0.05 μm, for example, over the entire surface of the glass substrate 2 using the PCVD equipment. Next, a Ti thin film layer 34, for example, as a heat-resistant metal layer about 0.1 μm thick, an Al thin film layer 35 as a low-resistance wire layer about 0.3 μm thick, and a Ti thin film layer 36, for example, as an intermediate conductive layer about 0.1 μm thick, namely, source-drain wire material are successively deposited using the SPT or other vacuum film-depositing equipment. Drain electrodes 21 of insulating gate-type transistors and signal lines 12 doubling as source electrodes are selectively formed. But in this selective patterning, it is a major feature of the streamlined four-mask process to form photosensitive resin patterns 80A and 80B thinner than the 3 μm of source-drain wiring formation regions 80A(12) and 80A(21) with the channel formation region 80B (oblique portion) between the source-drain 1.5 μm thick, for example, as shown in FIG. 14(b) and FIG. 15(b) using half-tone exposure technology.
For such photosensitive resin patterns 80A and 80B, a positive photosensitive resin is ordinarily used in the production of substrates for liquid crystal display devices, so a black, that is, a thin Cr film is formed for the source-drain wire formation region 80A, a gray line and space Cr pattern is formed with a width of 0.5 to 1 μm, for example, for the channel region 80B, and for other regions, a photo-mask may be used to make them white, that is, remove the thin Cr film. It is possible to transmit about half of the photo-mask passing light from a lamp source because the lines and spaces are not resolved due to inadequate exposure resolution, so the photosensitive resin patterns 80A and 80B may be obtained in the gray region having a concave cross-section shape such as that shown in FIG. 15(b) corresponding to the residual film properties of the positive-type photosensitive resin. By forming a MoSi2 thin film, for example, rather than a Cr thin film slit in the gray region, a photo-mask with an equivalent function may be obtained.
After successively etching the Ti thin film layer 36, the Al thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 using the said photosensitive plastic patterns 80A and 80B as masks to expose the gate insulating layer 30 as shown in FIG. 15(b), the photosensitive resin patterns 80A and 80B are decreased at least 1.5 μm by ashing means such as oxygen plasma, eliminating the photosensitive resin patterns 80B to expose the channel regions, and leaving the photosensitive resin patterns 80C (12) and 80C (21) unchanged only on the source-drain wire formation regions as shown in FIG. 14(c) and FIG. 15(c). Then, the Ti thin film layer, Al thin film layer, Ti thin film layer, second amorphous silicon layer 33A, and first amorphous silicon layer 31A are successively etched again using the reduced photosensitive resin patterns 80C (12) and 80C (21) as masks, and then the first amorphous silicon layer 31A is etched leaving around 0.05 to 0.1 μm. After the metal layer is etched, the first amorphous silicon layer 31A is etched leaving around 0.05 to 0.1 μm, forming the source-drain wires, so the insulating gate-type transistor obtained with such a method is referred to as a channel-etch. The resist pattern 80A is reduced so as to be converted to 80C in the said oxygen plasma treatment, so it is desirable to strengthen the anisotropicity to suppress changes in the pattern dimensions. In further detail, RIE (Reactive Ion Etching) oxygen plasma treatment is desirable, and ICP (Inductive Coupled Plasma) or TCP (Transfer Coupled Plasma) oxygen plasma treatment with a higher density plasma source is even more desirable.
After removing the said photosensitive resin patterns 80C (12) and 80C (21), a second SiNx layer about 0.3 μm thick is deposited as a transparent insulating layer over the entire surface of the glass substrate 2 to make a passivation insulating layer 37 as same as prior five-mask process; openings 62, 63, and 64 are formed on the drain electrodes 21 and in regions to be formed for the electrode terminals for the scan lines 11 and for the signal lines 12, respectively using a photosensitive resin pattern with micro-fabrication technology as shown in FIG. 14(d) and FIG. 15(d); the gate insulating layer 30 and the passivation insulating layer 37 in the openings 63 are removed to expose part 5 of the scan lines; and the passivation insulating layer 37 in the openings 62 and 64 are removed to expose part of the drain electrodes 21 and part 6 of the signal lines. Similarly, openings 65 are formed on the storage capacitor lines 16 to expose part thereof.
Finally, ITO or IZO, for example, is deposited as a transparent conductive layer about 0.1 to 0.2 μm thick using an SPT or other vacuum film-depositing equipment, and transparent conductive pixel electrodes 22 containing the openings 62 are selectively formed on the passivation insulating layer 37 using a photosensitive resin pattern with micro-fabrication technology to complete the active substrate 2 as shown in FIG. 14(e) and FIG. 15(e). For the electrode terminals, transparent conductive electrode terminals 5A and 6A made from ITO are selectively formed on the passivation insulating layer 37 containing the openings 63 and 64.